1. Field of Invention
The present invention generally relates to voltage generating circuit, and more particularly to a voltage generating circuit with improved boosting efficiency.
2. Description of Prior Art
A voltage generating circuit which generates a higher voltage than the supplied power voltage source is widely used in memory devices, such as flash memory. for programming the memory content. Providing a power voltage source with a constant high voltage level is one of the solutions for writing memory devices, but this solution has poor power efficiency since only the writing procedure requires the high voltage level. Thus, providing a voltage generating circuit in the memory device is an appropriate solution.
The U.S. Pat. No. 5,043,858 provides a high-voltage generating circuit for generating a high voltage from a power voltage source. Referring to FIGS. 1 and 2, FIG. 1 is a circuit diagram of the high-voltage generating circuit 10, and FIG. 2 is a waveform diagram of the high-voltage generating circuit 10. The high-voltage generating circuit comprises a series circuit 1 composed of a plurality of field effect transistors M0˜Mn connected in series between a power voltage terminal VCC and a high-voltage output terminal VOUT, a plurality of capacitors C1˜Cn with one end connected to intermediate nodes of the field effect transistors M0˜Mn, and first and second clock signal generators 2, 2′ for generating first and second clock signals CL1, CL2 with higher level than the power voltage and different phases. The first and second clock signals CL1, CL2 having different phases are applied alternatively to the other ends of these adjacent capacitors C1˜Cn respectively.
The high-voltage generating circuit 10 needs a clock signal φ to generate four control signals φ1˜φ4 with different, non-overlapping phases. See FIG. 2, the four control signals φ1˜φ4 should be generated precisely to be non-overlap at the high voltage level, and thus it increases the complexity of generating the four control signals φ1˜φ4. Additionally, in FIG. 2, the duty cycle of first and second clock signals CL1, CL2 at high level voltage, 3V, is 25%. In some applications, the requirement of duty cycle may be larger than 0.25, thus it may not be adapted in some applications.
The U.S. Pat. No. 6,480,057 provides a voltage doubling circuit which can generate a high-level voltage from the power voltage source. Referring to FIGS. 3 and 4, FIG. 3 is a circuit diagram of a voltage doubling circuit 30, and FIG. 4 is a waveform diagram of the voltage doubling circuit 30. The voltage doubling circuit 30 is composed of two inverters 41, 42, a capacitor 43, three p-type metal-oxide-semiconductor (PMOS) transistors 44, 45, 46, and two n-type metal-oxide-semiconductor (NMOS) transistors 47, 48. The voltage doubling circuit 30 generates a clock signal CLK2′ having amplitude doubled to power supply voltage CLK2's (as shown in FIG. 4). The clock signal CLK2′ is applied to the gate of the NMOS transistor connected to the external capacitor. Thus, by increasing the gate voltage of the NMOS transistor, the resistance of the NMOS transistor connected to the external capacitor is sufficiently reduced and transfer efficiency of positive charge is enhanced.
Since the feedback paths exist in the transistors 45, 44, and 47, and the leak current also incurs in the voltage doubling circuit 30, thus the time of charging the capacitor of the voltage doubling circuit 30 to the predetermined level increases. Therefore, the transient time of the voltage doubling circuit 30 may increase. In the high speed circuit application, the voltage doubling circuit 30 may not be an appropriate choice.
In order to reduce the complexity and delay time of the voltage generating circuit, the embodiment of the invention provides a voltage generating circuit with less circuit complexity to generate an output clock signal.